1. Field of the Invention
The invention relates to an etching process useful in the manufacture of integrated circuit structures. More particularly, the invention relates to an etch process for the removal of photoresist residues present on a dielectric stack and on the inside walls of microvias formed in a dielectric layer on a semiconductor substrate.
2. Related Art
In the production of integrated circuits (IC's), a semiconductor substrate is provided with a series of layers comprising conductive lines and dielectric materials. The design of VLSI and ULSI chips involves the use of multiple levels of metal interconnects to connect active areas of the chip together. Conductive lines on opposite sides of a dielectric surface are interconnected by means of metals deposited in microvias in the dielectric. These interconnects have typically been composed of Al, W, polysilicon and Si/Al/Cu composites but may also include copper in newer generations of microchips. Metal lines are insulated by non-conducting materials, typically SiO.sub.2 but may also have SiO.sub.2 /polymer dielectric combinations or polymer dielectric only. Such polymer dielectrics include spin-on glasses, and low dielectric constant polymers such as spin-on polymers, nanoporous silicas, and organic polymer insulators. The SiO.sub.2 /polymer dielectric layers insulate the metal lines and also impart structural integrity to the entire interconnect level allowing for the next interconnect level to be placed on top of the existing level. The number of such interconnect levels is increasing and will continue to increase as the dimensions of microchips decrease.
The many levels of metal lines are interconnected through holes or microvias which electrically connect metal lines on one level with metal lines on higher or lower levels. The vias are filled with conducting metals and pass through the polymer dielectric layers of the interconnect level to the metal line on the next interconnect level. The formation of these vias is therefore a critical factor in determining proper performance of the microchip device. Photolithographic processes, which use photoimageable materials to fabricate built-up IC's have been developed for via formation. In these processes, photoresists are coated onto a substrate and photoimaged to define via holes. The formation of a via involves several processing steps, one of which involves the removal of photoresist after the via has been patterned and etched by plasma chemistries. It is necessary to remove such residues from the microvias since, when such residues are present in microvias, they degrade interconnect and barrier layer deposition and performance. The photoresist, which remains on the portions of the circuit structure after patterning, has been conventionally removed by ashing or removal of the photoresist by excited oxygen species generated in a plasma. The usual processing occurs at high pressures and temperatures, often above 200.degree. C. These oxygen species can, however, also attack material such as organic and inorganic polymer dielectrics. This attack results in a poor via profile and oxidation/hydration of the polymer dielectric resulting in high via resistance and poor chip performance.
Ashing techniques are generally preferred over wet etch techniques since the underlying metals are not attacked, and because ashing is sometimes more effective in removal of photoresist residues, particularly when the photoresist has been altered by reactive ion etching, high temperature post bakes, or the like. However, while prior ashing techniques are able to remove photoresists from the surface of a dielectric, they have been found to be less than satisfactory in removing photoresist residues from the inside walls of microvias through the polymer dielectrics. In addition, for polymer dielectrics, since prior art plasma processes used to remove residues have been conducted at high temperatures, there has been a tendency to shrink the films, oxidize the films, cause a degradation of the dielectric constant or cause water absorption which outgases during subsequent processing steps such as depositing barrier layers or interconnect metals. Other processes such as those which use H.sub.2 and N.sub.2 plasmas reduce such problems but remove the photoresist at a lower than desired rate.
U.S. Pat. No. 5,382,316 describes a process for the removal of photoresist residues from an integrated circuit structure using a plasma etch gas mixture of oxygen, water vapor and a fluorine containing gas. The process removes photoresist and etch residues from a substrate surface. There is no teaching of photoresist removal from vias in surface dielectrics. U.S. Pat. No. 5,174,856 describes a process for removing photoresist and chlorine containing residues remaining over a metal layer after etching of the metal layer on an integrated circuit structure. This is done by conducting a stripping step using either O.sub.2 gas, O.sub.2 gas and N.sub.2 gas and/or a fluorocarbon gas plasma followed by a subsequent step using a combination of O.sub.2 and NH3 gases. There is also no teaching of photoresist removal from vias in surface dielectrics. U.S. Pat. No. 5,824,604 teaches photoresist stripping using a plasma of an oxidizing gas, a fluorine containing compound and a hydrocarbon. The process preferentially strips photoresist from a substrate with little etching of oxide on the substrate surface. As in the patents described above, there is also no teaching of photoresist removal from vias. Other low temperature, non-damaging via ashing alternatives exist through the use of low temperature, low pressure reactive ion etch (RIE) tools. These, however, constitute a higher capital investment option.
It would be desirable to provide an improved process for the removal of photoresist remaining after microvia formation which would not only remove the photoresist mask from a dielectric surface on a substrate, but also remove any photoresist residues present on the inside walls of the microvias formed in a dielectric layer containing polymer dielectrics. A process would be desired which would also strip the photoresist at a commercially acceptable rate and which would reduce the tendency to shrink and oxidize the film and degrade the dielectric constant and cause water absorption of the polymer dielectric exposed in the via side wall.